Behavioral design and test assistance for pipelined processors

H. Iwashita, T. Nakata, F. Hirose
{"title":"Behavioral design and test assistance for pipelined processors","authors":"H. Iwashita, T. Nakata, F. Hirose","doi":"10.1109/ATS.1992.224427","DOIUrl":null,"url":null,"abstract":"The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224427","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<>
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
流水线处理器的行为设计和测试辅助
作者提出了一种设计和测试处理器的新概念。这种方法在VHDL中为特定的处理器机制生成行为级测试环境,包括测试程序和行为描述的自动生成。作者实现了一个管道控制器的应用程序。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Localization and aftereffect of automatic test generation A practical approach for the diagnosis of a MIMD network A complement-based fast algorithm to generate universal test sets for combinational function blocks A control constrained test scheduling approach for VLSI circuits Techniques for reducing hardware requirement of self checking combinational circuits
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1