N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong
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引用次数: 156
Abstract
Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well
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