Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure

Abstract

We report on the development of a fast characterization technique of EEPROM tunnel oxides based on the floating-gate technique and using a realistic memory cell-based test structure. A sequential measurement procedure and data analysis have been successfully implemented to perform automatic wafer screening of leakage currents in terms of charge retention and tunnel oxide defectivity.