Hyunpil Noh, Suock Jeong, Seongjoon Lee, Yousung Kim, Woncheol Cho, M. Huh, G. Jeong, J. Suh, Hoyeop Kweon, J. Roh, Kisoo Shin, Sangdon Lee
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引用次数: 1
Abstract
The first 8F/sup 2/ stack DRAM cell with 0.08 /spl mu/m/sup 2/ size has been successfully integrated by employing a poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. The cell transistor with W gate technology exhibits sufficient saturation current (I/sub OP/) of /spl sim/40 /spl mu/A with threshold voltage (V/sub tsat/) of 0.9 V and satisfactory ring oscillator delay characteristics of /spl sim/50 ps.
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