Darren Aaberge, K. Mockler, Dieu Van Dinh, R. Belleau, Tim Donovan, R. Hewlitt
{"title":"Meeting the test challenges of the 1 Gbps parallel RapidIO/spl reg/ interface with new automatic test equipment capabilities","authors":"Darren Aaberge, K. Mockler, Dieu Van Dinh, R. Belleau, Tim Donovan, R. Hewlitt","doi":"10.1109/VTS.2005.55","DOIUrl":null,"url":null,"abstract":"This paper describes an approach to testing the 1 Gbps Parallel RapidIO/spl reg/ interface specifications. The unique test requirements for this bus require the application of new test techniques as well as new ATE capabilities. ATE performance attributes important for parallel source-synchronous buses will be identified and presented with methods to measure these attributes.","PeriodicalId":268324,"journal":{"name":"23rd IEEE VLSI Test Symposium (VTS'05)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"23rd IEEE VLSI Test Symposium (VTS'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2005.55","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper describes an approach to testing the 1 Gbps Parallel RapidIO/spl reg/ interface specifications. The unique test requirements for this bus require the application of new test techniques as well as new ATE capabilities. ATE performance attributes important for parallel source-synchronous buses will be identified and presented with methods to measure these attributes.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
