High performance on-chip interconnect system supporting fast SoC generation

Abstract

As VLSI technology continuously scales and market requirements from embedded SoC rapidly change, there is a growing need for on-chip interconnect that fits high performance multiprocessor systems and allows fast SoC generation to reduce time to market. Historically, most of the on-chip interconnects were based on a shared bus architecture, connecting a plurality of masters and a plurality of slaves. This approach becomes obsolete as technology performance increases, due to limited scalability and huge circuit design effort involved. On the other hand, the approach, which proposes non-ordered packet-based interconnect (network on a chip) cannot fulfil the need for latency-sensitive on-chip interconnect and implies complex design and verification. Focusing on high performance multiprocessors systems, addressing the need for fast SoC generation and keeping design and verification efficient, the chip level arbitration and switching system (CLASS), designed by Freescale Semiconductor, proposes a complete on-chip interconnect system which addresses the challenges in today's SoC architectures