K. Lee, H.J. Shin, J.W. Hwang, S.W. Nam, Y.J. Moon, Y. Wee, I.G. Kim, W. Park, J.H. Kim, S.J. Lee, K.K. Park, H. Kang, K. Suh
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引用次数: 3
Abstract
A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).
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