{"title":"Flash memory reliability","authors":"A. Modelli, A. Visconti","doi":"10.1109/IRWS.2005.1609590","DOIUrl":null,"url":null,"abstract":"Summary form only given. Memory reliability is a key issue of flash technology. The continuous trend to increase the storage density is driving the technology close to its physical limits and new reliability challenges are met. The tutorial discussed the failure mechanisms limiting memory endurance and data retention. Reference was made to the two mainstream flash technologies, considering a floating-gate cell in a NOR- or NAND-type memory array. The first part of the tutorial was dedicated to failure modes related to the intrinsic cell behavior. Classical data loss mechanisms and the degradation of the oxide properties caused by high-field tunneling or channel hot electron injection were examined. The second part dealt with single-cell failures, in particular low-temperature data loss after program/erase cycling, which can be ascribed to tunnel oxide defects. The nature of the leakage current and its relation with the stress-induced leakage current observed in large area capacitors was discussed. Design solutions to solve, or at least ease, this issue was considered.","PeriodicalId":214130,"journal":{"name":"2005 IEEE International Integrated Reliability Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"37","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Integrated Reliability Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRWS.2005.1609590","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 37
Abstract
Summary form only given. Memory reliability is a key issue of flash technology. The continuous trend to increase the storage density is driving the technology close to its physical limits and new reliability challenges are met. The tutorial discussed the failure mechanisms limiting memory endurance and data retention. Reference was made to the two mainstream flash technologies, considering a floating-gate cell in a NOR- or NAND-type memory array. The first part of the tutorial was dedicated to failure modes related to the intrinsic cell behavior. Classical data loss mechanisms and the degradation of the oxide properties caused by high-field tunneling or channel hot electron injection were examined. The second part dealt with single-cell failures, in particular low-temperature data loss after program/erase cycling, which can be ascribed to tunnel oxide defects. The nature of the leakage current and its relation with the stress-induced leakage current observed in large area capacitors was discussed. Design solutions to solve, or at least ease, this issue was considered.