{"title":"A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection","authors":"H. Tomiye, T. Terano, K. Nomoto, T. Kobayashi","doi":"10.1109/VLSIT.2002.1015454","DOIUrl":null,"url":null,"abstract":"We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
We have proposed a novel 2-bit/cell MONOS memory structure that features a wrapped gate. Programming and erasing are by source-side hot-electron injection and hot-hole injection, respectively. With this device, programming speeds <1 /spl mu/s with a programming current <2 /spl mu/A//spl mu/m, and erasing speeds <10 /spl mu/s have been achieved.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
