M. Okazaki, M. Hatano, K. Yoshida, S. Shibasaki, H. Kaneko, T. Yoda, N. Hayasaka
{"title":"\"Sea of Kelvin\" multiple-pattern arrangement interconnect characterization for low-k/Cu dual damascene and its findings","authors":"M. Okazaki, M. Hatano, K. Yoshida, S. Shibasaki, H. Kaneko, T. Yoda, N. Hayasaka","doi":"10.1109/IITC.2004.1345749","DOIUrl":null,"url":null,"abstract":"A very unique multiple pattern arrangement for low-k/Cu interconnect characterization method is introduced. Several hundreds of different shape 4-point probe Kelvin/via/interconnect test patterns are created. With these \"Sea of Kelvin\" multiple-pattern test structures, 65nm node generation feature size (0.10/spl mu/m /spl phi/ via). Low-k/Cu dual damascene interconnect is evaluated. Various aspects of pattern design dependent interconnect characteristics including the influence from the surrounding neighbour patterns are examined. This paper reports this new characterization method and its findings.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2004.1345749","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A very unique multiple pattern arrangement for low-k/Cu interconnect characterization method is introduced. Several hundreds of different shape 4-point probe Kelvin/via/interconnect test patterns are created. With these "Sea of Kelvin" multiple-pattern test structures, 65nm node generation feature size (0.10/spl mu/m /spl phi/ via). Low-k/Cu dual damascene interconnect is evaluated. Various aspects of pattern design dependent interconnect characteristics including the influence from the surrounding neighbour patterns are examined. This paper reports this new characterization method and its findings.