Minimum verification test set for combinational circuit

H. Michinishi, T. Yokohira, T. Okamoto
{"title":"Minimum verification test set for combinational circuit","authors":"H. Michinishi, T. Yokohira, T. Okamoto","doi":"10.1109/ATS.1992.224428","DOIUrl":null,"url":null,"abstract":"A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2/sup w/ elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2/sup w/ elements for any CUT with up to four outputs is described.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224428","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2/sup w/ elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2/sup w/ elements for any CUT with up to four outputs is described.<>
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组合电路的最小验证测试集
推导了组合电路具有2/sup w/个单元的最小验证测试集(MVTS)的充分条件,其中w为任何输出所依赖的最大输入数,并描述了对于任何最多有四个输出的CUT,寻找具有2/sup w/个单元的最小验证测试集的算法
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Localization and aftereffect of automatic test generation A practical approach for the diagnosis of a MIMD network A complement-based fast algorithm to generate universal test sets for combinational function blocks A control constrained test scheduling approach for VLSI circuits Techniques for reducing hardware requirement of self checking combinational circuits
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