A combined R/sub G//C/sub F/ large-signal extraction methodology to improve CMOS SPICE-parameter precision

Abstract

This paper presents a simple and efficient parameter extraction methodology, based on time-domain large-signal measurements of two ring oscillators as test structures. This experimentally confirmed technique is a new tool for determining the parasitic gate resistance R/sub G/ and for a fine tuning of the fringing capacitance C/sub F/ of MOS transistors in one step. Thus CMOS switching speed can be predicted more accurately, compared to conventional parameter tuning methodologies and the expenditure of SPICE parameter extractions can be reduced.