Design Migration from Peripheral ASIC Design to Area-IO Flip-Chip Design by Chip I/O Planning and Legalization

Abstract

Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style, compared with peripheral bonding style in packaging consideration