Analysis of Intermittent Single-bit Failure on 10-nm node generation DRAM Devices

Abstract

The intermittent single-bit (SB) failure is one of the most important problems in DRAM technology development because it is almost impossible to reproduce and screen out. In this paper, the intermittent SB failure was analyzed theoretically. Based on our physical modeling, we suggested several technical methods to reduce the intermittent SB failure and got the experimental results that decrease the intermittent SB failure rate. Furthermore, we predicted the failure rate based on our theoretical model. The SB failure rate had over 85% consistency between prediction and results. Therefore, we proved that our failure modeling is appropriate for predicting the occurrence of the intermittent SB failure. Furthermore, we can propose the design of the next generation DRAM technology to achieve equivalent or better intermittent SB quality than the previous generation from the beginning of the development.