Degradation of rise time in NAND gates using 2.0 nm gate dielectrics

Abstract

CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and an increase in threshold voltage by 18% are directly proportional to an increase in channel resistance, thereby substantially increasing the NAND gate circuit timing delay.