Reliability characterization of interconnects in CMOS integrated circuits under mechanical stress

Abstract

Integrated circuits are often subjected to mechanical stress resulting from external loads or intrinsic stress caused by the mismatch in thermal expansion coefficients of the applied materials. Interconnects and vias in these circuits are particularly jeopardized when applied in complementary metal-oxide semiconductor (CMOS)-based microelectromechanical systems (MEMS). In this paper, we characterize the reliability of interconnects using a heterogeneous CMOS/MEMS monitor chip manufactured using deep reactive ion etching. It comprises various daisy-chain structures with different combinations of interconnects integrated in a thin silicon membrane hinge subjected to tensile mechanical stress. The electro-mechanical testing is performed using a custom-made system that simultaneously applies mechanical stress and performs mechanical and electrical measurements. Experiments provide somewhat unexpected insight into patterns of failure of different types of interconnects.