Impact of gate stack processing on the hysteresis of 300 mm integrated WS2 FETs

Abstract

The low quality of gate dielectrics deposited on 2D channels and the resulting poor reliability of 2D FETs are major issues that need to be addressed as a high priority. In this work, we compare 300 mm integrated dual-gate WS2 FETs with two different interlayers (SiOx and AlOx) in the top HfO2 -based gate stack by means of hysteresis measurements. The collected data enable the extraction of essential properties of defects in the gate oxide, which are commonly recognized as the main cause of instability of 2D FETs. In particular, the hysteresis width is evaluated as a function of the measurement sweep rate in order to investigate the time constants of the dominant defects in both interlayers. Finally, a new measurement-simulation scheme to extract the energy distribution of defects causing hysteresis is proposed. We observe that defects in AlOx-capped devices have slower capture/emission time constants and much lower energy density approaching the conduction band minimum of the channel than those in SiOx. Therefore, A1Ox reduces hysteresis and improves reliability compared to SiOx.