Physical origin of Vt instabilities in high-k dielectrics and process optimisation

Abstract

The continuous scaling down of SiO/sub 2/ gate oxide is bound to reach its physical limits owing to gate leakage and reliability concerns. High-k dielectrics have been identified to replace the conventional SiO/sub 2/ as gate dielectrics materials. One of the main concerns which could be show-stopper for a successful integration of these new materials is the Vt instability relating to electron trapping. In this paper we discuss the origin of the electron traps. Based on a review of literature results and new experimental data, we demonstrate that this instability can be reduced by process optimization.