A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low-k ILD interconnects on 300 mm wafers

C. Jan, N. Anand, C. Allen, J. Bielefeld, M. Buehler, V. Chikamane, K. Fischer, K. Jain, J. Jeong, S. Klopcic, T. Marieb, B. Miner, P. Nguyen, A. Schmitz, M. Nashner, T. Scherban, B. Schroeder, C. Ward, R. Wu, K. Zawadzki, S. Thompson, M. Bohr
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引用次数: 7

Abstract

A leading edge 90 nm, 300 mm wafer size interconnect technology featuring Cu, CDO low-k ILD and industry's most aggressive 220 nm minimum metal pitch is being ramped into production for high performance Pentium/spl reg/ microprocessors, the first in industry, to our knowledge. Key enabling features for yield and reliability improvement to resolve challenges from weak thermo-mechanical properties of low k ILD and tight metal pitches for a production worthy interconnect process are presented.
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90nm高容量制造逻辑技术,在300mm晶圆上实现铜金属化和CDO低k ILD互连
据我们所知,一种领先的90纳米、300毫米晶圆尺寸的互连技术,具有Cu、CDO低k ILD和业界最具侵略性的220纳米最小金属间距,正在投入生产,用于高性能奔腾/spl reg/微处理器,这在业界尚属首次。提出了提高成品率和可靠性的关键功能,以解决低k ILD和紧密金属节距的弱热机械性能带来的挑战,从而实现具有生产价值的互连工艺。
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