M. Motoyoshi, K. Moriyama, H. Mori, C. Fukumoto, H. Itoh, H. Kano, K. Bessho, H. Narisawe
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引用次数: 5
Abstract
This work is a report on high-performance MRAM technology. 0.4/spl times/0.8 /spl mu/m/sup 2/ MTJ elements were successfully integrated with 0.35 /spl mu/m CMOS technology without process-induced damage. A magnetoresistance (MR) ratio of more than 55% and the read/write operating point were obtained by introducing an improved magnetic tunnel junction (MTJ) material. The short-pulse writing in combination with an improved cell structure suggests that MRAM has a great deal of potential for low power applications.
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