Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress

E. Cartier, A. Kerber
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引用次数: 97

Abstract

The stress-induced leakage current (SILC) in nFETs with SiO2/HfO2/TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, Ea ∼ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (Vt) instability ΔIg/Ig ∼ dVt3. Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and Vt-degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO2 defects –such as oxygen vacancy – and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the Vt instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.
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在正偏置温度应力下,HfO2/TiN栅极堆nfet的应力诱发漏电流和缺陷产生
研究了金属电极SiO2/HfO2/TiN双介质栅极晶体管在高温和高栅极应力电压下的应力诱发漏电流(SILC)。结果表明,在HfO2中产生的强缺陷导致了SILC随应力时间的线性增加。发现SILC生成是热激活的,活化能为Ea ~ 1ev。此外,SILC的形成与阈值电压(Vt)不稳定性ΔIg/Ig ~ dVt3有很强的相关性。这两种退化现象都表现出很强的滞后行为;通过施加负栅偏压,观察到应力后SILC和vt的退化大大减少。所有这些观察结果都可以从氢氧化氢浅层缺陷(如氧空位)中的电荷捕获和应力过程中新浅层缺陷的产生来解释。缺陷生成过程具有较低的活化能,可能是由于薄膜效应。因此,在加速TDDB试验条件下,SILC和Vt不稳定性较大。研究还表明,观察到的低活化能结合SILC的可逆性对双介电栅堆叠的介电击穿检测具有重要意义。
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