R. Singanamalla, C. Ravit, G. Vellianitis, J. Pétry, V. Paraschiv, J. van Zijl, S. Brus, M. Verheijen, R. Weemaes, M. Kaiser, J. van Berkum, P. Bancken, R. Vos, H. Yu, K. De Meyer, S. Kubicek, S. Biesemans, J. Hooker
{"title":"Low VT Mo(O,N) metal gate electrodes on HfSiON for sub-45nm pMOSFET Devices","authors":"R. Singanamalla, C. Ravit, G. Vellianitis, J. Pétry, V. Paraschiv, J. van Zijl, S. Brus, M. Verheijen, R. Weemaes, M. Kaiser, J. van Berkum, P. Bancken, R. Vos, H. Yu, K. De Meyer, S. Kubicek, S. Biesemans, J. Hooker","doi":"10.1109/IEDM.2006.346864","DOIUrl":null,"url":null,"abstract":"We report band-edge pFET threshold voltage (V<sub>t</sub> ~ 0.28 V) for MoO<sub>x</sub>N<sub>y</sub> on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs V<sub>t</sub> of 0.45 V using a MoO <sub>x</sub>/SiON gate stack, meeting the requirement for 45nm high-V <sub>t</sub> CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoO<sub>x</sub>/SiON and MoO<sub>x</sub>/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoO<sub>x</sub>N<sub>y</sub> gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using both MoOx/SiON and MoOx/HfSiON gate stacks. Excellent dielectric integrity is also shown for devices with MoOxNy gated stack such as device mobility, NBTI and TDDB characteristics, as compared to our base-line poly/SiON devices
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