SRAM Cell Static Noise Margin and VMIN Sensitivity to Transistor Degradation

Abstract

The SRAM cell sensitivity to transistor degradation is understood using a novel test methodology. A new, semi-empirical model that captures the observed trends is derived. The key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/ high PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly from the mean VTP shift which moves the overall distribution, and (c) NBTI-induced variance is overwhelmed by the time-zero variation of the six transistors of the SRAM. These findings enable a quantitative prediction that the NBTI-induced VMIN increase during burn-in is of the order of the NBTI-induced VT shift