Impact of Barrier Metal Thickness on SRAM Reliability

Abstract

To understand the effect of barrier metal thickness (BM THK) of metal gate (MG) on static random access memory (SRAM) reliability, we evaluated 3 different wafer-level reliability (WLR) methods; random telegraph noise (RTN) characteristics ($\tau_{\mathrm{c}}/\tau_{\mathrm{e}}$, or capture/ emission time constant) and BTI recovery are studied on single-bit transistors, and SRAM static noise margin (SNM) degradation is also investigated with various stress configuration. Using three different MG process splits, it is observed that RTN performance is modulated by BM THK. Through BM THK optimization, the best result (i.e., $\mathbf{RTN}\downarrow$, bias temperature instability (BTI) $\mathbf{recovery}\uparrow$, SRAM SNM $\mathbf{shift}\downarrow$) could be achieved, owing to less oxide damage by minimal trapping/de-trapping phenomenon. This clearly indicates the need of subtle process-reliability optimization. In addition, high temperature operating life (HTOL) is performed to confirm the SRAM Vmin shift at package-level test.