{"title":"Suppression of Cu extrusion into porous-MSQ film during chip-reliability test","authors":"Hiroshi, Satoshi Kageyama, Shigeydu Katayama, Naofumi Ohashi, Yoshihisa Matsubara, Nobuyoshi Kobayashi","doi":"10.1109/IITC.2004.1345673","DOIUrl":null,"url":null,"abstract":"We have found that Cu-line walls located along the peripheral of the test chips improve lifetime in chip-level electromigration (EM) test and time-dependent dielectric breakdown (TDDB) test for Cu/porous-methyl-silsesquioxane (MSQ) structure. After EM test at elevated temperatures, Cu loss and extrusion are greatly suppressed in the samples with the walls. They seem to be promoted by any reactants such as moisture or oxidant penetrated from the surface on the chip side and to cause short EM lifetime. Therefore, the above layout is effective and essential in future Cu/low-k integrity.","PeriodicalId":148010,"journal":{"name":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2004.1345673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We have found that Cu-line walls located along the peripheral of the test chips improve lifetime in chip-level electromigration (EM) test and time-dependent dielectric breakdown (TDDB) test for Cu/porous-methyl-silsesquioxane (MSQ) structure. After EM test at elevated temperatures, Cu loss and extrusion are greatly suppressed in the samples with the walls. They seem to be promoted by any reactants such as moisture or oxidant penetrated from the surface on the chip side and to cause short EM lifetime. Therefore, the above layout is effective and essential in future Cu/low-k integrity.
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