Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling

Abstract

In this study a Finite Element Model (FEM) was designed in order to predict the reliability behavior of 7×7 mm2 Wafer Level Chip Scale Packages (WLCSP) during board level thermal cycling tests, considering different solder material models for SAC405 and SACQ interconnects. A significant difference in plastic strains within the package was observed for a variety of solder material models: Compared to SACQ interconnects an approximate 70% plastic strain increase in solder and a 35% plastic strain reduction in the polyimide passivation layer was observed for packages with SAC405 interconnects. Simulations were verified by experimental thermal cycling test data done at board level. During thermal cycling, packages showed different failure modes depending on the interconnect material used in the package. Also, SAC405 showed earlier failure. Maximum strain obtained from simulations was used as an indicator of potential failure locations for the solder alloy and polyimide layer. The proposed model setup enables precise simulation results, which are well aligned with the actual experimental findings on the behavior of WLCSP with SAC405 and SACQ interconnects.