A robust and production worthy addressable array architecture for deep sub-micron MOSFET's matching characterization

Abstract

A robust addressable array test structure is presented, which allows automated characterization of the MOSFET's matching, with high area and time efficiency, accuracy and repeatability. It features CMOS switches to ensure a full test operation range, and prevent gate oxide breakdown of individual DUTs from destroying the functionality of the whole test structure. The test structure provides superior isolation to minimize cross talk while providing greater flexibility in testing. The testing result (Id mismatch) on wafers of 0.18 /spl mu/m technology is presented.