Back end reliability [IC interconnections]

Abstract

Summary form only given. As interconnects become responsible for a larger portion of signal delays in advanced circuits the pressure for aggressive scaling will increase. Current densities will increase as dimensions are reduced and stress management will be more critical as the compliance of low-k materials decreases. However, reducing the interconnect dimensions tend to degrade reliability as the critical volume associated with a failure decreases. This talk reviewed the conflicting requirements for reliability and product performance and the solutions that are being pursued. Several paths are available for improving electromigration including advanced barriers, copper alloy seed layers and metallic cap layers. However, each of these solutions will come at the cost of line resistance, which is already increasing due to increased scattering in small geometries. Stress migration will become a larger concern at small dimensions because both the absolute stress level and stress gradients will increase at smaller geometries. Reducing the density of the inter-level dielectric will exaggerate these problems due to intrinsically lower adhesion energies and an increased diffusivity of copper, water and ammines in the dielectric. Ultimately, it will be reliability that limits the scaling of interconnects for future nodes.