Optimization of the buffer thickness for high performance 1 /spl mu/m gate GaAs MESFETs on InP substrate for OEICs

Abstract

GaAs/InP FETs on InP appear to be promising for the realization of optoelectronic integrated circuits (OEICs) for low and high bit-rate optical communication. However, there are two fundamental problems, the 3.9% lattice mismatch and 210/sup -6///spl deg/C difference in thermal expansion coefficients leading to the formation of a high density of dislocations and to a high level of tensile stress in the GaAs layer. For possible applications it is mandatory to investigate the effect of this mismatch through the buffer thickness on the DC and microwave performance of GaAs/InP MESFETs. An improvement in the DC and microwave performance of GaAs MESFETs on InP substrate has been observed when increasing the undoped GaAs buffer thickness. For a 3 /spl mu/m thick GaAs buffer, the 1 /spl mu/m gate MESFET has a maximum extrinsic transconductance larger than 230mS/mm, a current gain cut-off frequency of 15 GHz, a maximum frequency of oscillation of 28 GHz, a minimum noise figure of 1 dB at 4 GHz and a Hooge parameter of 2.5 10/sup -5/. Such results clearly indicate the potential of GaAs/InP MESFETs for application to OEICs.<>