Predictive simulation to improve reliability of a snapback-based NMOS clamp

Abstract

To incorporate high current electro-static discharge (ESD) conditions, we have extended a NMOS SPICE model to include models of a parasitic BJT, body (substrate) resistance and impact ionization current. The approach taken models the geometry and layout dependence of the NMOS, making the model scalable. The developed model predicts trigger voltages of MOS and BJT qualitatively and with reasonable accuracy. Clamps having longer body to source spacing are seen to trigger the parasitic BJT faster, irrespective of the MOS channel length. The parasitic BJT device parameters do not have significant effect on the clamp turn-on voltage