ELFIN (elevated field insulator) and SEP (S/D elevated by poly-Si plugging) process for ultra-thin SOI MOSFETs with high performance and high reliability

Abstract

The ELFIN (elevated field insulator) process for device isolation and SEP (source/drain elevated by poly-Si plugging) process for elevated S/D structure is developed for ultra-thin SOI MOSFETs with SOI films of less than 20 nm. With the ELFIN process, the gate electric field at the SOI edge is negligible as the SOI edge is not wrapped around by the poly-Si gate so that the reverse narrow channel effect of the NMOSFET is improved by about 50%, gate leakage current decreased by about 30%, and hot-carrier immunity increased by about 20%. With the SEP process, an elevated S/D region 60 nm thick is obtained so that S/D resistance is deceased to a third and has excellent uniformity over a wafer.