K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, J. Maes
{"title":"The mechanism of mobility degradation in MISFETs with Al/sub 2/O/sub 3/ gate dielectric","authors":"K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, J. Maes","doi":"10.1109/VLSIT.2002.1015446","DOIUrl":null,"url":null,"abstract":"We believe that the most important task in the development of high-/spl kappa/ gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, Al/sub 2/O/sub 3/ would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al/sub 2/O/sub 3/ gate dielectrics in sub-100 nm-FETs has already been demonstrated; however, the resulting electron mobility was only a quarter the value for a FET with SiO/sub 2/ gate dielectric (D. Buchanan et al., Tech. Digest IEDM, p. 223, 2000; J.H. Lee et al., ibid., p. 645, 2000). We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.","PeriodicalId":103040,"journal":{"name":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2002.1015446","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
We believe that the most important task in the development of high-/spl kappa/ gate dielectrics is to engineer the interface to assure high enough mobility and reliability. Considering the 100-nm node, Al/sub 2/O/sub 3/ would appear to be the most promising candidate in terms of chemical and thermal stability, barrier offset, and compatibility with the conventional CMOS process. The integration of Al/sub 2/O/sub 3/ gate dielectrics in sub-100 nm-FETs has already been demonstrated; however, the resulting electron mobility was only a quarter the value for a FET with SiO/sub 2/ gate dielectric (D. Buchanan et al., Tech. Digest IEDM, p. 223, 2000; J.H. Lee et al., ibid., p. 645, 2000). We have clarified the mechanism by which mobility is thus degraded, both experimentally and theoretically.
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