Integration of high performance dual workfunction logic CMOS transistors with a dense 8F/sup 2/ vertical DRAM cell

Abstract

In this paper, we report on integration of high performance dual workfunction logic CMOS transistors with a commodity 8F/sup 2/ vertical DRAM cell for high performance stand-alone DRAM and low-cost low-power embedded DRAM applications. Key process integration features that exploit novel aspects of the vertical DRAM cell to enable a high performance embedded DRAM technology are presented. The impact of pre-metal-dielectric reflow thermal budget on dual workfunction CMOS device characteristics is discussed.