TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates

Abstract

Extensive breakdown measurements with large statistic confirm that the TDDB failure distribution follows Poisson area scaling. However, towards larger areas and lower failure percentiles the distribution changes in ways similar to those reported for progressive breakdown in poly Si/SiON gate stacks. The change in failure distribution is found to be more pronounced for nFET than for pFET devices. In addition AC TDDB testing was explored, confirming the shape of the DC failure distributions but shows a significant reduction in TDDB lifetime for nFET devices.