T. Ernst, C. Dupré, C. Isheden, É. Bernard, R. Ritzenthaler, V. Maffini-Alvaro, J. Barbe, F. de Crécy, A. Toffoli, C. Vizioz, S. Borel, F. Andrieu, V. Delaye, D. Lafond, G. Rabillé, J. Hartmann, M. Rivoire, B. Guillaumot, A. Suhm, P. Rivallin, O. Faynot, G. Ghibaudo, S. Deleonibus
{"title":"Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack","authors":"T. Ernst, C. Dupré, C. Isheden, É. Bernard, R. Ritzenthaler, V. Maffini-Alvaro, J. Barbe, F. de Crécy, A. Toffoli, C. Vizioz, S. Borel, F. Andrieu, V. Delaye, D. Lafond, G. Rabillé, J. Hartmann, M. Rivoire, B. Guillaumot, A. Suhm, P. Rivallin, O. Faynot, G. Ghibaudo, S. Deleonibus","doi":"10.1109/IEDM.2006.346955","DOIUrl":null,"url":null,"abstract":"Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"269 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"56","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 56
Abstract
Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties of this novel 3D architecture are explored: (i) HfO2/TiN gate stack is integrated, (ii) electrons and holes mobilities are measured on 150 beams matrices (3 levels) and compared to those of planar transistors (hi) a sub-100nm channel width is demonstrated and (iv) specific 3D integration challenges like zipping between nano-beams are discussed
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