Practical considerations in ATPG using CrossCheck technology

Proceedings First Asian Test Symposium (ATS `92) Pub Date : 1992-11-26 DOI:10.1109/ATS.1992.224441

S. Chandra, N. Jacobson, G. Srinath

引用次数: 4

Abstract

The authors deal with some of the practical considerations that arise in porting ATPG patterns to the tester. Issues such as races, bidirectional pins, three-state buses and asynchronous circuits are discussed. Algorithm for dealing with these constructs during the test pattern generation phase are presented. Patterns that correctly handle such situations are easily ported to the tester. Experimental results on real circuits are presented. The results also include ATE resources such as tester time and memory required for the test program. The circuits are assumed to adhere to the CrossCheck design-for-testability methodology.<>

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

在ATPG使用交叉检查技术的实际考虑

作者处理了在将ATPG模式移植到测试器中出现的一些实际问题。讨论了竞赛、双向引脚、三态总线和异步电路等问题。给出了在测试模式生成阶段处理这些构造的算法。正确处理这种情况的模式很容易移植到测试人员身上。给出了在实际电路上的实验结果。结果还包括ATE资源，如测试程序所需的测试时间和内存。假设电路遵循交叉检查设计可测试性方法

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

Proceedings First Asian Test Symposium (ATS `92)

自引率

0.00%

发文量

期刊最新文献

Localization and aftereffect of automatic test generation A practical approach for the diagnosis of a MIMD network A complement-based fast algorithm to generate universal test sets for combinational function blocks A control constrained test scheduling approach for VLSI circuits Techniques for reducing hardware requirement of self checking combinational circuits