A new test structure and characterization methodology to identify array leakage path in Mask ROM

Abstract

The array leakage is a crucial issue while developing ultra high-density planar Mask ROM memories. However, it is hard to identify this leakage and its mechanism using the conventional cell array test structure. It is because that because the cell surface punch leakage, cell bulk leakage, and surface buried drain to buried drain (BD to BD) leakage beyond cell channel region all contribute to the total leakage at the same time. In order to identify these leakage paths and reduce this leakage, we design a new cell array test structure and the characterization methodology is also proposed. The main mechanism of cell leakage has been attributed to the surface BD to BD leakage outside the cell array. This leakage path occurs beneath the exposed silicon surface, which doping concentration near this region is lower than that inside the cell array due to oxide spacer over-etching issue and our PMOS blank N-type pocket implantation.