Poly-Si gate CMOSFETs with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric for low power applications

Abstract

For the first time, we have integrated poly-Si gate CMOS-FETs with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric (EOT=14.6 /spl Aring/) grown by Atomic Layer Deposition (ALD). The gate leakage currents are 3.7 /spl mu/A/cm/sup 2/ (Vg=+1.0 V) for nMOSFET and 0.2 /spl mu/A/cm/sup 2/ (Vg=-1.0 V) for pMOSFET. These extremely low leakage currents sufficiently satisfy the specification (EOT= 12/spl sim/20 /spl Aring/, Jg=2.2 mA/cm/sup 2/) estimated by ITRS. The fixed charge is decreased using HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric, and consequently flatband voltage (Vfb) shift is within 0.20 V compared with the Vfb of nitrided SiO/sub 2/ control. In addition, a low gate induced drain leakage (GIDL) is obtained using HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric. I/sub on/ vs. I/sub off/ plots of the planar CMOS transistor with high-k is shown for the first time in this paper. The measured saturation currents at 1.2 V Vdd are 430 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for nMOSFET and 160 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET. These are the highest currents compared with previous reports for the planar poly-Si gate CMOSFETs with high-k gate dielectric.