T. Hayashi, Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara, M. Inoue, J. Yugami, J. Tsuchimoto, K. Shiga, N. Murata, H. Sayama, T. Yamashita, H. Oda, T. Kuroi, T. Eimori, Y. Inoue
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引用次数: 3
Abstract
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability. It is demonstrated that this cost-worthy process provides performance which is competitive to reported dual metal CMOS
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