Improved short circuit performance of silicon carbide VD-MOSFETs using a P+ implant

Abstract

We show that the short circuit withstand time, t_SC, of a silicon carbide (SiC) Vertically Double-diffused Metal Oxide Semiconductor Field Effect Transistor (VD-MOSFET) can be raised using a P⁺ implant near the p-base corner of the device. Under short circuit conditions, this implant depletes the JFET region thereby reducing the peak short circuit current, I_SC, and consequently the lattice temperature. Hence, it takes a longer time for the peak device temperature to reach the failure threshold of ~1500 K. On the other hand, under normal on-state operation (when the drain to source voltage, V_DS, is low, ⁓20 V, V_GS = 20 V), P⁺ implant must deplete only an acceptably low fraction of the JFET width so that the on-state current remains unaffected. The window size, depth and dose of the implant can be optimized to yield the highest t_SC while simultaneously limiting the specific on-resistance, R_onsp. With the help of TCAD simulations calibrated with experiments, we show that the t_SC of a 0.6 kV device can be raised from 2.74 μs to 19 μs while restraining the rise in R_onsp within 12 % using a technologically feasible P⁺ double implant. SiC devices with the proposed implant can be switched using available gate drivers of Si IGBT and thus adopted in the industry readily.