Impact of Bias Condition on Electron Radiation Response of SiC MOSFETs

Abstract

The impact of bias voltage on the radiation effect of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) was studied using 1-MeV high-energy electrons. The results indicate that the device undergoes ionization effects during irradiation, resulting in a shift in the threshold voltage. At high fluence, the device also experiences displacement damage (DD) effects, leading to a decrease in saturation region current, linear region current, and linear region slope. Defects were characterized using deep-level transient spectroscopy (DLTS). The results demonstrate that during irradiation, the gate bias voltage promotes the formation of oxide charges. The gate bias voltage and drain bias voltage will affect the formation and evolution of defects within the bulk of the device. Through technology computer-aided design (TCAD) simulation, it was determined that deep-level defects are the primary contributors to the current decrease in the device, and oxide charges are the main cause of the threshold voltage shift. The simulation results are largely consistent with experimental findings, indicating that the presence of drain bias during irradiation enhances the DD effect. Furthermore, the presence of gate bias exacerbates both ionization damage and DD.