Economics of semiconductor scaling - a cost analysis for advanced technology node

Abstract

Moore's law, the principle that has powered semiconductor scaling for the past 50 years is nearing its end. However, the industry would like to pursue a dimensional scaling roadmap to reap the full benefit of technology innovation. Results shown on this paper demonstrate traditional dimensional scaling approaches involving multi-patterned lithography would skyrocket the manufacturing cost. Design level techniques collectively known as scaling boosters, and innovative Complementary FET (CFET) devices would help to reduce the cost of the technology nodes. To the best of our knowledge, this is the first approach where semiconductor node transitions are benchmarked based on their economic feasibility. To summarize, we have formulated a cost-driven approach that can guide the industry to continue semiconductor scaling.