Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776533
A. Saha, B. Grisafe, S. Datta, S. Gupta
In this paper, we theoretically and experimentally investigate the Zr concentration dependent crystal phase transition of Hf1-xZxO2 (HZO) and the corresponding evolution of dielectric (DE), ferroelectric (FE) and anti-ferroelectric (AFE) characteristics. Providing the microscopic insights of strain induced crystal phase transformations, we propose a physics based model that shows good agreement with our experimental results for 10nm Hf1-xZxO2 (with $text{x}=0$ through 1). Utilizing our model, we analyze HZO-FET operation as a non-volatile memory device for different x.
{"title":"Microscopic Crystal Phase Inspired Modeling of Zr Concentration Effects in Hf1-xZrxO2Thin Films","authors":"A. Saha, B. Grisafe, S. Datta, S. Gupta","doi":"10.23919/VLSIT.2019.8776533","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776533","url":null,"abstract":"In this paper, we theoretically and experimentally investigate the Zr concentration dependent crystal phase transition of Hf<inf>1-</inf><inf>x</inf>Z<inf>x</inf>O<inf>2</inf> (HZO) and the corresponding evolution of dielectric (DE), ferroelectric (FE) and anti-ferroelectric (AFE) characteristics. Providing the microscopic insights of strain induced crystal phase transformations, we propose a physics based model that shows good agreement with our experimental results for 10nm Hf<inf>1-x</inf>Z<inf>x</inf>O<inf>2</inf> (with <tex>$text{x}=0$</tex> through 1). Utilizing our model, we analyze HZO-FET operation as a non-volatile memory device for different x.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"83 1","pages":"T226-T227"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74064598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776548
X. Lyu, M. Si, X. Sun, M. Capano, H. Wang, Peide D. Ye
The ferroelectric (FE) and anti-ferroelectric (AFE) properties of hafuium zirconium oxide (HZO) are investigated systematically down to 3 nm. The ferroelectric polarization, switching speed and the impact of atomic layer deposited (ALD) tungsten nitride (WN) electrodes are studied. Record high remnant polarization $(text{P}_{r})$, on FE HZO and record high saturation polarization $(text{P}_{s})$ on AFE HZO are achieved with WN electrodes, especially in ultrathin sub-10 nm regime. A high dielectric constant of 30.4 is achieved on AFE HZO. The polarization switching speed of FE and AFE HZO, associated with C-V frequency dispersion, are also studied. For the first time, it is found polarization switching speed is faster in AFE HZO than FE HZO, suggesting AFE-FET could be more promising for high speed memory devices.
{"title":"Ferroelectric and Anti-Ferroelectric Hafnium Zirconium Oxide: Scaling Limit, Switching Speed and Record High Polarization Density","authors":"X. Lyu, M. Si, X. Sun, M. Capano, H. Wang, Peide D. Ye","doi":"10.23919/VLSIT.2019.8776548","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776548","url":null,"abstract":"The ferroelectric (FE) and anti-ferroelectric (AFE) properties of hafuium zirconium oxide (HZO) are investigated systematically down to 3 nm. The ferroelectric polarization, switching speed and the impact of atomic layer deposited (ALD) tungsten nitride (WN) electrodes are studied. Record high remnant polarization $(text{P}_{r})$, on FE HZO and record high saturation polarization $(text{P}_{s})$ on AFE HZO are achieved with WN electrodes, especially in ultrathin sub-10 nm regime. A high dielectric constant of 30.4 is achieved on AFE HZO. The polarization switching speed of FE and AFE HZO, associated with C-V frequency dispersion, are also studied. For the first time, it is found polarization switching speed is faster in AFE HZO than FE HZO, suggesting AFE-FET could be more promising for high speed memory devices.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"52 1","pages":"T44-T45"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78913358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776478
S. Song, B. Colombeau, M. Bauer, V. Moroz, X. Lin, P. Asenov, D. Sherlekar, M. Choi, J. Huang, B. Cheng, C. Chidambaram, S. Natarajan
We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics representative of artificial intelligence (AI) applications. The design rules correspond to 2nm node with cell heights of 100~110 nm and 30 nm gate pitch. Holistic analysis of the RO (Ring Oscillator) behavior, including MOL parasitics, all major variability sources, and stress proximity effects suggests that different FinFET and nanoslab transistor design options exhibit a wide range of power and performance differences. The key to improve FinFET PPA is to avoid fin cuts to maintain strong PMOS performance, and a key to improve SS corner delay is to use nanoslabs with tighter variability control.
{"title":"2nm Node: Benchmarking FinFET vs Nano-Slab Transistor Architectures for Artificial Intelligence and Next Gen Smart Mobile Devices","authors":"S. Song, B. Colombeau, M. Bauer, V. Moroz, X. Lin, P. Asenov, D. Sherlekar, M. Choi, J. Huang, B. Cheng, C. Chidambaram, S. Natarajan","doi":"10.23919/VLSIT.2019.8776478","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776478","url":null,"abstract":"We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics representative of artificial intelligence (AI) applications. The design rules correspond to 2nm node with cell heights of 100~110 nm and 30 nm gate pitch. Holistic analysis of the RO (Ring Oscillator) behavior, including MOL parasitics, all major variability sources, and stress proximity effects suggests that different FinFET and nanoslab transistor design options exhibit a wide range of power and performance differences. The key to improve FinFET PPA is to avoid fin cuts to maintain strong PMOS performance, and a key to improve SS corner delay is to use nanoslabs with tighter variability control.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"136 1","pages":"T206-T207"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78241742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776551
W. Kim, R. Bruce, T. Masuda, G. Fraczak, N. Gong, P. Adusumilli, S. Ambrogio, H. Tsai, J. Bruley, J.-P. Han, M. Longstreet, F. Carta, K. Suu, M. BrightSky
We have demonstrated, for the first time, a combination of outstanding linearity of analog programming with matched PCM pairs, small analog programming noise, an extremely low resistance drift (R-drift) coefficient (0.005, median) and high endurance for a CVD-based confined phase change memory (PCM) with a thin metallic liner. In-depth analysis of linear analog programming is also presented. MNIST simulations using a pair of these confined PCM devices as a synaptic element yield a high test accuracy of 95%.
{"title":"Confined PCM-based Analog Synaptic Devices offering Low Resistance-drift and 1000 Programmable States for Deep Learning","authors":"W. Kim, R. Bruce, T. Masuda, G. Fraczak, N. Gong, P. Adusumilli, S. Ambrogio, H. Tsai, J. Bruley, J.-P. Han, M. Longstreet, F. Carta, K. Suu, M. BrightSky","doi":"10.23919/VLSIT.2019.8776551","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776551","url":null,"abstract":"We have demonstrated, for the first time, a combination of outstanding linearity of analog programming with matched PCM pairs, small analog programming noise, an extremely low resistance drift (R-drift) coefficient (0.005, median) and high endurance for a CVD-based confined phase change memory (PCM) with a thin metallic liner. In-depth analysis of linear analog programming is also presented. MNIST simulations using a pair of these confined PCM devices as a synaptic element yield a high test accuracy of 95%.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"2 2-3 1","pages":"T66-T67"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72793297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776543
Shuo-Mao Chen, M. Yew, F. Hsu, Y.J. Huang, Y. Lin, M.S. Liu, K.C. Lee, P. Lai, T. Lai, Shin-Puu Jen
The fan-out packaging technology has recently been adopted in mobile application processors due to its advantages in form factor, fine pitch traces, and efficient thermal dissipation. This paper demonstrates heterogeneous integration on a fan-out redistribution layer (RDL) interposer. The package has a full-reticle size Si die and two HBMs. Si die and memory modules are attached to a fanout RDL and are then attached to a multilayer substrate. This advanced package meets both electrical and mechanical requirements. The fanout RDL interposer is comprised of polymer and copper traces, and it is relatively mechanically flexible. Such flexibility enhances C4 joint integrity, and allows the new package to scale up its size to meet more complex functional demands.
{"title":"High Performance Heterogeneous Integration on Fan-out RDL Interposer","authors":"Shuo-Mao Chen, M. Yew, F. Hsu, Y.J. Huang, Y. Lin, M.S. Liu, K.C. Lee, P. Lai, T. Lai, Shin-Puu Jen","doi":"10.23919/VLSIT.2019.8776543","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776543","url":null,"abstract":"The fan-out packaging technology has recently been adopted in mobile application processors due to its advantages in form factor, fine pitch traces, and efficient thermal dissipation. This paper demonstrates heterogeneous integration on a fan-out redistribution layer (RDL) interposer. The package has a full-reticle size Si die and two HBMs. Si die and memory modules are attached to a fanout RDL and are then attached to a multilayer substrate. This advanced package meets both electrical and mechanical requirements. The fanout RDL interposer is comprised of polymer and copper traces, and it is relatively mechanically flexible. Such flexibility enhances C4 joint integrity, and allows the new package to scale up its size to meet more complex functional demands.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"197 1","pages":"T52-T53"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72909582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776583
C. Jin, T. Saraya, T. Hiramoto, M. Kobayashi
We have investigated transient $I_{text{d}}-V_{text{g}}$ and $I_{text{d}}-V_{text{d}}$ characteristics of ferroelectric FET (FeFET) by simulation with ferroelectric (FE) model considering polarization switching dynamics. For the first time, we show transient negative capacitance (TNC) with polarization reversal and depolarization effect results in sub-60 SS, reverse drain-induced barrier lowering (R-DIBL), and negative differential resistance (NDR) without traversing the quasi-static negative capacitance (QSNC) region in S-shaped P-Vbased on Landau theory. The mechanism demonstrated in this work can be a possible explanation for the previously reported negative capacitance FET (NCFET) with steep SS, R-DIBL, and NDR.
{"title":"Transient Negative Capacitance as Cause of Reverse Drain-induced Barrier Lowering and Negative Differential Resistance in Ferroelectric FETs","authors":"C. Jin, T. Saraya, T. Hiramoto, M. Kobayashi","doi":"10.23919/VLSIT.2019.8776583","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776583","url":null,"abstract":"We have investigated transient $I_{text{d}}-V_{text{g}}$ and $I_{text{d}}-V_{text{d}}$ characteristics of ferroelectric FET (FeFET) by simulation with ferroelectric (FE) model considering polarization switching dynamics. For the first time, we show transient negative capacitance (TNC) with polarization reversal and depolarization effect results in sub-60 SS, reverse drain-induced barrier lowering (R-DIBL), and negative differential resistance (NDR) without traversing the quasi-static negative capacitance (QSNC) region in S-shaped P-Vbased on Landau theory. The mechanism demonstrated in this work can be a possible explanation for the previously reported negative capacitance FET (NCFET) with steep SS, R-DIBL, and NDR.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"6 3","pages":"T220-T221"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72583518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776558
E. Capogreco, H. Arimura, L. Witters, A. Vohra, C. Porret, R. Loo, A. De Keersgieter, E. Dupuy, D. Marinov, A. Hikavyy, F. Sebaai, G. Mannaert, L. Ragnarsson, Y. Siew, C. Vrancken, A. Opdebeeck, J. Mitard, R. Langer, E. Sanchez, F. Holstetns, S. Demuynck, K. Barla, V. De Heyn, D. Mocuta, N. Collaert, N. Horiguchi
This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(text{L}_{text{G}}sim 25text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $text{L}_{text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.
本文展示了高性能的张力p型双堆叠Ge gate - ali - around (GAA)器件，与我们之前的工作相比，栅极长度$(text{L}_{text{G}}sim 25text{nm})$显著减少。通过采用无扩展方案，在$text{L}_{text{G}}=25$ nm的范围内保持良好的静电控制，同时通过适当的间隔缩放和采用高b掺杂的Ge或GeSn作为源/漏极(S/D)材料来保持性能。
{"title":"High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG","authors":"E. Capogreco, H. Arimura, L. Witters, A. Vohra, C. Porret, R. Loo, A. De Keersgieter, E. Dupuy, D. Marinov, A. Hikavyy, F. Sebaai, G. Mannaert, L. Ragnarsson, Y. Siew, C. Vrancken, A. Opdebeeck, J. Mitard, R. Langer, E. Sanchez, F. Holstetns, S. Demuynck, K. Barla, V. De Heyn, D. Mocuta, N. Collaert, N. Horiguchi","doi":"10.23919/VLSIT.2019.8776558","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776558","url":null,"abstract":"This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(text{L}_{text{G}}sim 25text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $text{L}_{text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"43 1","pages":"T94-T95"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85929218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776580
Kihyun Choi, H. Sagong, Wonchang Kang, Hyunjin Kim, J. Hai, Miji Lee, Bomi Kim, Miji Lee, Soonyoung Lee, H. Shim, Junekyun Park, Youngwoo Cho, H. Rhee, S. Pae
In this paper, we report the reliability characterization of 7nm FinFET technology, in which the highly scaled 6th generation of FinFETs and 256Mbit SRAM cells was newly developed by utilizing EUV. The single EUV patterning of MOL and BEOL resulted in significantly improved reliability distribution as compared to the previous nodes with multiple patterning techniques. The successful demonstration on product reliability including SRAM, Logic HTOL, and SER as technology evaluation was performed, indicating the 7nm technology+EUV is ready for high volume manufacturing.
{"title":"Enhanced Reliability of 7nm Process Technology featuring EUV","authors":"Kihyun Choi, H. Sagong, Wonchang Kang, Hyunjin Kim, J. Hai, Miji Lee, Bomi Kim, Miji Lee, Soonyoung Lee, H. Shim, Junekyun Park, Youngwoo Cho, H. Rhee, S. Pae","doi":"10.23919/VLSIT.2019.8776580","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776580","url":null,"abstract":"In this paper, we report the reliability characterization of 7nm FinFET technology, in which the highly scaled 6th generation of FinFETs and 256Mbit SRAM cells was newly developed by utilizing EUV. The single EUV patterning of MOL and BEOL resulted in significantly improved reliability distribution as compared to the previous nodes with multiple patterning techniques. The successful demonstration on product reliability including SRAM, Logic HTOL, and SER as technology evaluation was performed, indicating the 7nm technology+EUV is ready for high volume manufacturing.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"13 1","pages":"T16-T17"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78919494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776496
S. L. Liu, J. Horng, Amit Akundu, Y. Hsu, B. Lien, S. F. Liu, C. W. Chang, H. Hsieh, D. Huang, Y. C. Peng, Sally Liu, Mark Chen
This paper presents a 3D thermal impedance network approach to study self-heating effects in advanced FinFETs that are difficult to be analyzed in conventional models: (i) temperature distribution analysis for large FinFET devices used in high current drivers (ii) transient thermal modeling for heat accumulation in GHz digital circuits, and (iii) investigation for layout methods to reduce FinFET self-heating temperature.
{"title":"Self-Heating Temperature Behavior Analysis for DC - GHz Design Optimization in Advanced FinFETs","authors":"S. L. Liu, J. Horng, Amit Akundu, Y. Hsu, B. Lien, S. F. Liu, C. W. Chang, H. Hsieh, D. Huang, Y. C. Peng, Sally Liu, Mark Chen","doi":"10.23919/VLSIT.2019.8776496","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776496","url":null,"abstract":"This paper presents a 3D thermal impedance network approach to study self-heating effects in advanced FinFETs that are difficult to be analyzed in conventional models: (i) temperature distribution analysis for large FinFET devices used in high current drivers (ii) transient thermal modeling for heat accumulation in GHz digital circuits, and (iii) investigation for layout methods to reduce FinFET self-heating temperature.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T200-T201"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85740636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776520
Xuewei Feng, Yida Li, Lin Wang, Z. Yu, Shuai Chen, W. Tan, Nasiruddin Macadam, G. Hu, X. Gong, T. Hasan, Yong-Wei Zhang, A. Thean, K. Ang
We demonstrate the first fully-printed resistive random access memory (RRAM) on flexible substrate using 2D layered dichalcogenides, exhibiting ultra-low switching voltage down to 0.18 V and an on/off ratio up to 107. The novel switching medium is printed by formulating multilayer molybdenum disulfide (MoS2) into 3D-printable ink. Both volatile and non-volatile resistive switching are achieved within a single device by varying current compliance, which enables the implementation of electronic synapse with neuromorphic functionality including short-term plasticity (STP) and long-term plasticity (LTP).
{"title":"First Demonstration of a Fully-Printed Mos2Rram on Flexible Substrate with Ultra-Low Switching Voltage and its Application as Electronic Synapse","authors":"Xuewei Feng, Yida Li, Lin Wang, Z. Yu, Shuai Chen, W. Tan, Nasiruddin Macadam, G. Hu, X. Gong, T. Hasan, Yong-Wei Zhang, A. Thean, K. Ang","doi":"10.23919/VLSIT.2019.8776520","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776520","url":null,"abstract":"We demonstrate the first fully-printed resistive random access memory (RRAM) on flexible substrate using 2D layered dichalcogenides, exhibiting ultra-low switching voltage down to 0.18 V and an on/off ratio up to 107. The novel switching medium is printed by formulating multilayer molybdenum disulfide (MoS2) into 3D-printable ink. Both volatile and non-volatile resistive switching are achieved within a single device by varying current compliance, which enables the implementation of electronic synapse with neuromorphic functionality including short-term plasticity (STP) and long-term plasticity (LTP).","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T88-T89"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88209727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：