W. Lien, W.G. Yeh, C.H. Li, K. Tu, I.H. Chang, H. Chu, W.R. Liaw, H.F. Lee, H. Chou, C.Y. Chen, M.H. Chi
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引用次数: 7
Abstract
A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.
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