Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001567
C.H. Li, K. Tu, H. Chu, I.H. Chang, W.R. Liaw, H.F. Lee, W. Lien, M. Tsai, W. Liang, W.G. Yeh, H. Chou, C.Y. Chen, M.H. Chi
In this paper, the effect of SiN pull-back process for shallow trench isolation (STI) is investigated by measuring DRAM array's refresh time (Tref) and yield as sensitive monitors. The SiN pull-back is performed by using H/sub 3/PO/sub 4/ solution after trench etch (i.e. before liner oxidation). For comparison, DRAMs were fabricated by using various isolation methods including LOCOS, conventional STI, and poly-buffered STI (PB-STI). The SiN pull-back process is known for reducing "divot" around the top comer in conventional STI. Both LOCOS and PB-STI can result in "divot" free. It is also known that "divot" will degrade the inverse narrow width effect of pass transistor and result in "double hump". In our study, SiN pull-back in STI indeed eliminates "double-hump" in I/sub d/-V/sub g/ curves of pass transistors. The SiN pull-back also can result in better data retention of DRAM than if without pull-back, but comparable to LOCOS and PB-STI. The optimized window of SiN pull-back in this study is 10 nm to 40 nm with best yield at 15 nm (slightly better yield than LOCOS and PB-STI).
{"title":"A robust shallow trench isolation (STI) with SiN pull-back process for advanced DRAM technology","authors":"C.H. Li, K. Tu, H. Chu, I.H. Chang, W.R. Liaw, H.F. Lee, W. Lien, M. Tsai, W. Liang, W.G. Yeh, H. Chou, C.Y. Chen, M.H. Chi","doi":"10.1109/ASMC.2002.1001567","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001567","url":null,"abstract":"In this paper, the effect of SiN pull-back process for shallow trench isolation (STI) is investigated by measuring DRAM array's refresh time (Tref) and yield as sensitive monitors. The SiN pull-back is performed by using H/sub 3/PO/sub 4/ solution after trench etch (i.e. before liner oxidation). For comparison, DRAMs were fabricated by using various isolation methods including LOCOS, conventional STI, and poly-buffered STI (PB-STI). The SiN pull-back process is known for reducing \"divot\" around the top comer in conventional STI. Both LOCOS and PB-STI can result in \"divot\" free. It is also known that \"divot\" will degrade the inverse narrow width effect of pass transistor and result in \"double hump\". In our study, SiN pull-back in STI indeed eliminates \"double-hump\" in I/sub d/-V/sub g/ curves of pass transistors. The SiN pull-back also can result in better data retention of DRAM than if without pull-back, but comparable to LOCOS and PB-STI. The optimized window of SiN pull-back in this study is 10 nm to 40 nm with best yield at 15 nm (slightly better yield than LOCOS and PB-STI).","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84435362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001632
R. Guldi, J. Shaw, J. Ritchison, S. Oestreich, K. Davis, R. Fiordalice
The introduction of copper dual Damascene processing into integrated circuits has brought about a host of new defectivity issues, especially those related to pitting and voiding. These defects must be understood and eliminated to achieve competitive manufacturing yields and assure device reliability.
{"title":"Characterization of copper voids in dual damascene processes","authors":"R. Guldi, J. Shaw, J. Ritchison, S. Oestreich, K. Davis, R. Fiordalice","doi":"10.1109/ASMC.2002.1001632","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001632","url":null,"abstract":"The introduction of copper dual Damascene processing into integrated circuits has brought about a host of new defectivity issues, especially those related to pitting and voiding. These defects must be understood and eliminated to achieve competitive manufacturing yields and assure device reliability.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80968894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001580
M. Ono, H. Iwata, K. Watanabe
We evaluated the accuracy of yield impact calculations based on kill ratio analysis. The accuracy was calculated using computer simulated defect maps and bin maps. The results show that the yield impact was inaccurate when parametric faults caused low yield or a large number of non-killer defects were included in inspection reports. It is therefore recommended to evaluate bin maps and reduce the non-killer defects before calculating the yield impact.
{"title":"Accuracy of yield impact calculation based on kill ratio","authors":"M. Ono, H. Iwata, K. Watanabe","doi":"10.1109/ASMC.2002.1001580","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001580","url":null,"abstract":"We evaluated the accuracy of yield impact calculations based on kill ratio analysis. The accuracy was calculated using computer simulated defect maps and bin maps. The results show that the yield impact was inaccurate when parametric faults caused low yield or a large number of non-killer defects were included in inspection reports. It is therefore recommended to evaluate bin maps and reduce the non-killer defects before calculating the yield impact.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78314621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001608
G. Baweja, B. Ouyang
With current high standards for product quality, reliability and performance, semiconductor manufacturers are constantly looking for ways and means to monitor and control the processes in real-time. The real-time control increases the equipment utilization and positively impacts the yields. The data collection is key to implementation of above strategy. This paper presents a comprehensive data collection methodology for the Real-time data acquisition system. This methodology addresses the physical and logical aspects of data collection system. The business needs and technical/process limitations of various approaches to deal with logical aspects have been discussed. The methodology is illustrated using examples from actual tools (parameters, algorithms to control the parameters, and business impact). The methodology presented in this paper has been deployed to over 200 processing tools from various vendors at Texas Instruments (TI).
{"title":"Data acquisition approach for real-time equipment monitoring and control","authors":"G. Baweja, B. Ouyang","doi":"10.1109/ASMC.2002.1001608","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001608","url":null,"abstract":"With current high standards for product quality, reliability and performance, semiconductor manufacturers are constantly looking for ways and means to monitor and control the processes in real-time. The real-time control increases the equipment utilization and positively impacts the yields. The data collection is key to implementation of above strategy. This paper presents a comprehensive data collection methodology for the Real-time data acquisition system. This methodology addresses the physical and logical aspects of data collection system. The business needs and technical/process limitations of various approaches to deal with logical aspects have been discussed. The methodology is illustrated using examples from actual tools (parameters, algorithms to control the parameters, and business impact). The methodology presented in this paper has been deployed to over 200 processing tools from various vendors at Texas Instruments (TI).","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77198610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001609
T. Massie
The challenge of staying competitive in the current business environment towards opportunities requires creativity and new extreme thinking. Teamwork and taking risks are imperative to success. Our Novellus equipment maintenance team in the IBM Microelectronics Division Burlington is continually finding creative methodologies over and above the Best Known Methods (BKM) to drive towards better business decisions that translate directly into productivity improvements. Whereas Mean Time to Repair (MTR) could go up due to increased in-house solutions, every effort is driven towards maintaining the equipment availability at target. In this presentation, I will discuss the methodologies the maintenance team deployed to stay at productivity target and yet manage the cost of ownership at reduced spending. Primarily, I will show hardware and software examples that the team saw to be opportunities for improvement.
{"title":"Semiconductor fab maintenance challenge and BKM in downturn economy","authors":"T. Massie","doi":"10.1109/ASMC.2002.1001609","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001609","url":null,"abstract":"The challenge of staying competitive in the current business environment towards opportunities requires creativity and new extreme thinking. Teamwork and taking risks are imperative to success. Our Novellus equipment maintenance team in the IBM Microelectronics Division Burlington is continually finding creative methodologies over and above the Best Known Methods (BKM) to drive towards better business decisions that translate directly into productivity improvements. Whereas Mean Time to Repair (MTR) could go up due to increased in-house solutions, every effort is driven towards maintaining the equipment availability at target. In this presentation, I will discuss the methodologies the maintenance team deployed to stay at productivity target and yet manage the cost of ownership at reduced spending. Primarily, I will show hardware and software examples that the team saw to be opportunities for improvement.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81670169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001579
C. Zhou, R. Ross, C. Vickery, B. Metteer, S. Gross, D. Verret
This paper presents methodologies for using critical area analysis with inline defect data to predict random defect limited yield and for partitioning yield losses by process step. The procedure involves (1) calculating critical areas, (2) modeling defect size distributions, and (3) combining critical area information and defect size distributions to estimate yield loss. We introduce a method to model defect size distribution from inline defect data. We develop two yield prediction methods that can overcome the difficulties caused by the inaccuracies in determining defect size when using laser scatterometry detection. We compare the predicted yield with the actual yield and show that the two are in good agreement.
{"title":"Yield prediction using critical area analysis with inline defect data","authors":"C. Zhou, R. Ross, C. Vickery, B. Metteer, S. Gross, D. Verret","doi":"10.1109/ASMC.2002.1001579","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001579","url":null,"abstract":"This paper presents methodologies for using critical area analysis with inline defect data to predict random defect limited yield and for partitioning yield losses by process step. The procedure involves (1) calculating critical areas, (2) modeling defect size distributions, and (3) combining critical area information and defect size distributions to estimate yield loss. We introduce a method to model defect size distribution from inline defect data. We develop two yield prediction methods that can overcome the difficulties caused by the inaccuracies in determining defect size when using laser scatterometry detection. We compare the predicted yield with the actual yield and show that the two are in good agreement.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76004068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001606
R. Islam, C. Brubaker, P. Lindner, C. Schaefer
The important factors for packaging technology are IC packaging costs, the impact of the package on circuit and system performance, and the reliability of the package. Wafer level packaging technology is a promising solution for future IC generations. This paper reviews the wafer level bumping process and its requirement for thick resist coating and full field aligned exposure. 3D interconnect technology is a viable solution for increasing electronic device functional density and reducing total packaging costs. The critical issue is the ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate. For CMOS devices, this technology can be applied to chip-scale packaging and also to advanced 3D interconnect processes. In this paper, we describe a new approach to wafer-to-wafer alignment using alignment targets at the bond interface, i.e. face to face wafer alignment (SmartVieW/sup TM/) that relies on precision alignment positioning systems to register and align wafers with one micron or better precision.
{"title":"Wafer level packaging and 3D interconnect for IC technology","authors":"R. Islam, C. Brubaker, P. Lindner, C. Schaefer","doi":"10.1109/ASMC.2002.1001606","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001606","url":null,"abstract":"The important factors for packaging technology are IC packaging costs, the impact of the package on circuit and system performance, and the reliability of the package. Wafer level packaging technology is a promising solution for future IC generations. This paper reviews the wafer level bumping process and its requirement for thick resist coating and full field aligned exposure. 3D interconnect technology is a viable solution for increasing electronic device functional density and reducing total packaging costs. The critical issue is the ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate. For CMOS devices, this technology can be applied to chip-scale packaging and also to advanced 3D interconnect processes. In this paper, we describe a new approach to wafer-to-wafer alignment using alignment targets at the bond interface, i.e. face to face wafer alignment (SmartVieW/sup TM/) that relies on precision alignment positioning systems to register and align wafers with one micron or better precision.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76118689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001607
N. Lafferty, B. Fiol, P. Jowett, Y. Karzhavin, T. Urenda
This paper discusses inline etch equipment qualification implementation at the 200 mm Infineon Technologies Richmond fab. Traditional etch equipment qualification requires offline etching of test blanket (or pattern) wafers of known thickness during a defined period. The process etch rate can be calculated using known film thickness and etch time. Data is obtained using an SPC system, which is then used to qualify the tool set. As a part of process control and data acquisition, time of etch is currently being monitored for automatic endpoint steps. The etch time is collected by an equipment integration software package, which communicates directly with the tool and records readings from sensors, step times, and other process conditions. The etch time is then combined with SPC gathered pre etch film thickness to determine an inline, on product, process etch rate. This gives the ability to monitor a chamber's performance without a costly break in the production for purposes of running a test wafer. This also allows instant detection of an out of control (OOC) process and prevents a significant scrap event.
{"title":"Equipment productivity improvement via inline qualification implementation","authors":"N. Lafferty, B. Fiol, P. Jowett, Y. Karzhavin, T. Urenda","doi":"10.1109/ASMC.2002.1001607","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001607","url":null,"abstract":"This paper discusses inline etch equipment qualification implementation at the 200 mm Infineon Technologies Richmond fab. Traditional etch equipment qualification requires offline etching of test blanket (or pattern) wafers of known thickness during a defined period. The process etch rate can be calculated using known film thickness and etch time. Data is obtained using an SPC system, which is then used to qualify the tool set. As a part of process control and data acquisition, time of etch is currently being monitored for automatic endpoint steps. The etch time is collected by an equipment integration software package, which communicates directly with the tool and records readings from sensors, step times, and other process conditions. The etch time is then combined with SPC gathered pre etch film thickness to determine an inline, on product, process etch rate. This gives the ability to monitor a chamber's performance without a costly break in the production for purposes of running a test wafer. This also allows instant detection of an out of control (OOC) process and prevents a significant scrap event.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87563723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001601
F. Pasqualini, E. Josse
Design of Experiments (DOE) is a structured approach widely used in the Microelectronics industry for over 20 years to study physical phenomena with simultaneous factors and responses. Today this methodology is in daily use to optimize process and products. With this in mind most DOE software's available on the market introduced since around five years ago have included the Desirability functions of Derringer (1980). Desirability functions permit the optimization simultaneously of several characteristics in the same experimental space. This first step in multi-response optimization was absolutely essential for industrial use of DOE, but this approach's weakness is that it is based on a deterministic optimization model. The provided optimum does not guarantee the robustness of the solution because it does not take into account uncertainty on factors and Response model coefficients. For this reason we are deploying at STMicroelectronics a multi-response optimization solution based on a stochastic approach of optimum's research. It takes into account uncertainty on factors and on coefficients of all the response models. The obtained solution provides a distribution function for the optimized criteria, which permits us to appreciate the statistically determined robustness. The different steps of optimization will be detailed. An example of application, for an advanced metal etch process in 0.18 /spl mu/m technology, will be presented. This permits us to point out the contribution of the stochastic solution to the process robustness and to compare it to the deterministic solution. In this example, the localization between optimums was different in the experimental space. The two solutions were tested and the physical results concluded that the better prediction was obtained with the stochastic optimum. The retained solution for industrialization was obviously the stochastic optimum.
{"title":"Robust optimization of experimental designs in microelectronics processes using a stochastic approach","authors":"F. Pasqualini, E. Josse","doi":"10.1109/ASMC.2002.1001601","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001601","url":null,"abstract":"Design of Experiments (DOE) is a structured approach widely used in the Microelectronics industry for over 20 years to study physical phenomena with simultaneous factors and responses. Today this methodology is in daily use to optimize process and products. With this in mind most DOE software's available on the market introduced since around five years ago have included the Desirability functions of Derringer (1980). Desirability functions permit the optimization simultaneously of several characteristics in the same experimental space. This first step in multi-response optimization was absolutely essential for industrial use of DOE, but this approach's weakness is that it is based on a deterministic optimization model. The provided optimum does not guarantee the robustness of the solution because it does not take into account uncertainty on factors and Response model coefficients. For this reason we are deploying at STMicroelectronics a multi-response optimization solution based on a stochastic approach of optimum's research. It takes into account uncertainty on factors and on coefficients of all the response models. The obtained solution provides a distribution function for the optimized criteria, which permits us to appreciate the statistically determined robustness. The different steps of optimization will be detailed. An example of application, for an advanced metal etch process in 0.18 /spl mu/m technology, will be presented. This permits us to point out the contribution of the stochastic solution to the process robustness and to compare it to the deterministic solution. In this example, the localization between optimums was different in the experimental space. The two solutions were tested and the physical results concluded that the better prediction was obtained with the stochastic optimum. The retained solution for industrialization was obviously the stochastic optimum.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85314803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001643
S.J. Hong, G. May
In this paper, neural networks trained by the error back-propagation algorithm are used to build models of etch rate, uniformity, selectivity and anisotropy as a function of optical emission spectroscopy (OES) data in a reactive ion etching process. The material etched is benzocyclobutene (BCB), a low-k dielectric polymer, which is etched in an SF/sub 6/ and O/sub 2/ plasma in a parallel plate system. Neural network training data are obtained from a multi-way principal component analysis (MPCA) of the OES data. These data are acquired from a 2/sup 4/ factorial experiment designed to characterize etch process variation with controllable input factors consisting of the two gas flows, RF power and chamber pressure. Evaluation of the trained neural networks is performed in terms of root mean square (RMS) error, and less than 3% prediction errors are achieved.
{"title":"Neural network modeling of reactive ion etching using principal component analysis of optical emission spectroscopy data","authors":"S.J. Hong, G. May","doi":"10.1109/ASMC.2002.1001643","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001643","url":null,"abstract":"In this paper, neural networks trained by the error back-propagation algorithm are used to build models of etch rate, uniformity, selectivity and anisotropy as a function of optical emission spectroscopy (OES) data in a reactive ion etching process. The material etched is benzocyclobutene (BCB), a low-k dielectric polymer, which is etched in an SF/sub 6/ and O/sub 2/ plasma in a parallel plate system. Neural network training data are obtained from a multi-way principal component analysis (MPCA) of the OES data. These data are acquired from a 2/sup 4/ factorial experiment designed to characterize etch process variation with controllable input factors consisting of the two gas flows, RF power and chamber pressure. Evaluation of the trained neural networks is performed in terms of root mean square (RMS) error, and less than 3% prediction errors are achieved.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89248726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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