A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors

Jin-Cheon Kim, Sanghoon Lee, Hong-June Park
{"title":"A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors","authors":"Jin-Cheon Kim, Sanghoon Lee, Hong-June Park","doi":"10.1109/ICVC.1999.820938","DOIUrl":null,"url":null,"abstract":"In this paper, a sense amplifier-based flip-flop (SAFF) with a fast output transition capability is proposed to reduce the pipeline overhead of high-performance microprocessors. The new SAFF overcomes the speed limitation of the conventional SAFF which is caused by the output latch implementation. The speed enhancement is achieved by reducing the number of gate stages to be passed from three to two. The SPICE simulation shows that the clock-to-output delay time of the new SAFF is enhanced by 63% compared to that of the conventional SAFF and the new SAFF has the fastest speed in comparison with the recently published flip-flops.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"83 1","pages":"384-387"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.820938","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In this paper, a sense amplifier-based flip-flop (SAFF) with a fast output transition capability is proposed to reduce the pipeline overhead of high-performance microprocessors. The new SAFF overcomes the speed limitation of the conventional SAFF which is caused by the output latch implementation. The speed enhancement is achieved by reducing the number of gate stages to be passed from three to two. The SPICE simulation shows that the clock-to-output delay time of the new SAFF is enhanced by 63% compared to that of the conventional SAFF and the new SAFF has the fastest speed in comparison with the recently published flip-flops.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一种基于感测放大器的CMOS触发器,具有增强的输出转换时间,用于高性能微处理器
为了减少高性能微处理器的流水线开销,提出了一种具有快速输出转换能力的基于感知放大器的触发器(SAFF)。新SAFF克服了由输出锁存器实现引起的传统SAFF的速度限制。速度的提高是通过将要通过的门级数量从三个减少到两个来实现的。SPICE仿真表明,与传统的触发器相比,新型触发器的时钟到输出延迟时间提高了63%,并且与最近发布的触发器相比,新型触发器具有最快的速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Plasma induced charging damage on thin gate oxide A 1.25-GBaud CMOS transceiver with on-chip terminator and voltage mode driver for Gigabit Ethernet 1000Base-X A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors Comparison of the characteristics of tunneling oxide and tunneling ON for p-channel nano-crystal memory Double precharge TSPC for high-speed dual-modulus prescaler
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1