Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820991
Jong-Yeol Lee, H. Yoon, Jin-Hyuk Yang, I. Park, C. Kyung
Code generation for embedded processors often encounters the problem of using complex instructions. The problems come from the heterogeneous register architecture of the embedded processors, small number of registers, and instructions with complex behaviors. In this paper we propose some techniques for using complex instructions. One of them is a simple technique to use MAC instruction (Modified Pattern Matching). The other two techniques are implemented in the Postpass Optimizer that optimizes the generated code with hardware loop instructions and post-increment or post-decrement addressing modes. Experimental results are also presented.
{"title":"Code generation for embedded processors with complex instructions","authors":"Jong-Yeol Lee, H. Yoon, Jin-Hyuk Yang, I. Park, C. Kyung","doi":"10.1109/ICVC.1999.820991","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820991","url":null,"abstract":"Code generation for embedded processors often encounters the problem of using complex instructions. The problems come from the heterogeneous register architecture of the embedded processors, small number of registers, and instructions with complex behaviors. In this paper we propose some techniques for using complex instructions. One of them is a simple technique to use MAC instruction (Modified Pattern Matching). The other two techniques are implemented in the Postpass Optimizer that optimizes the generated code with hardware loop instructions and post-increment or post-decrement addressing modes. Experimental results are also presented.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"35 1","pages":"525-528"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74665832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821012
Heon C. Kim, Dong-Soon Yi, Jin-Young Park, Chang-hyun Cho
This paper presents an efficient repair algorithm for embedded memory with multiple redundancies and a BISR (built-in self-repair) circuit using the proposed algorithm. While there are many repair algorithms which have good repair capability, their complexity is too high to implement. We present a repair algorithm which has good repair capability with little hardware overhead.
{"title":"A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies","authors":"Heon C. Kim, Dong-Soon Yi, Jin-Young Park, Chang-hyun Cho","doi":"10.1109/ICVC.1999.821012","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821012","url":null,"abstract":"This paper presents an efficient repair algorithm for embedded memory with multiple redundancies and a BISR (built-in self-repair) circuit using the proposed algorithm. While there are many repair algorithms which have good repair capability, their complexity is too high to implement. We present a repair algorithm which has good repair capability with little hardware overhead.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"24 1","pages":"602-605"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74795526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820820
Jun-Ha Lee, Seung-Woo Lee, J. Kong, Young-Wug Kim
We developed a new systematic calibration procedure which was applied to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity has been studied using 4 different groups of experimental conditions. Although the indium is susceptible to the TED, the RTA is effective to suppress the TED effect and maintain a steep retrograde profile. Like the boron, the indium shows significant oxidation-enhanced diffusion in silicon and has segregation coefficients at the Si/SiO/sub 2/ interface much less than 1. In contrast, however, the segregation coefficient of indium decreases as the temperature increases. The accuracy of the proposed technique is validated by SIMS data and 0.15-/spl mu/m device characteristics such as Vth and Idsat with errors less than 5% between simulation and experiment.
{"title":"Systematic calibration for transient enhanced diffusion of indium and its application to 0.15-/spl mu/m logic devices","authors":"Jun-Ha Lee, Seung-Woo Lee, J. Kong, Young-Wug Kim","doi":"10.1109/ICVC.1999.820820","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820820","url":null,"abstract":"We developed a new systematic calibration procedure which was applied to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity has been studied using 4 different groups of experimental conditions. Although the indium is susceptible to the TED, the RTA is effective to suppress the TED effect and maintain a steep retrograde profile. Like the boron, the indium shows significant oxidation-enhanced diffusion in silicon and has segregation coefficients at the Si/SiO/sub 2/ interface much less than 1. In contrast, however, the segregation coefficient of indium decreases as the temperature increases. The accuracy of the proposed technique is validated by SIMS data and 0.15-/spl mu/m device characteristics such as Vth and Idsat with errors less than 5% between simulation and experiment.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"37 1","pages":"53-56"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84884233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820875
Hyeon-deok Lee
Summary form only given, as follows. The interconnect system in ULSI has drawn greater attention nowadays than ever before. This is because the minimization of RC delay of interconnect has to be satisfied in order to achieve high performance of logic device in the GHz era. The major approach to lower RC delay has been directed toward integration of copper and low-k dielectric materials. In this paper, the current status of copper (barrier, seed, and electroplating) and low-k dielectric technologies and their integration issues are discussed.
{"title":"Interconnect technology: copper and low-k dielectrics","authors":"Hyeon-deok Lee","doi":"10.1109/ICVC.1999.820875","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820875","url":null,"abstract":"Summary form only given, as follows. The interconnect system in ULSI has drawn greater attention nowadays than ever before. This is because the minimization of RC delay of interconnect has to be satisfied in order to achieve high performance of logic device in the GHz era. The major approach to lower RC delay has been directed toward integration of copper and low-k dielectric materials. In this paper, the current status of copper (barrier, seed, and electroplating) and low-k dielectric technologies and their integration issues are discussed.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"6 1","pages":"201-"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76591277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820830
Kisun Kim, Kiyoung Choi, Young-Hyun Jun
Due to an efficient interconnect structure and internal parallelism, partitioned-bus architecture is viable for deep sub-micron chip design. In this paper, we propose a new partitioned-bus architecture and its supporting high-level synthesis methodology. The new architecture extends an existing linear architecture by stacking multiple layers for handling large datapath intensive applications. Experiments show that the approach generates compact datapath layout with flexibility of aspect ratio and reduces average bus driving length.
{"title":"Hardware synthesis for stack type partitioned-bus architecture","authors":"Kisun Kim, Kiyoung Choi, Young-Hyun Jun","doi":"10.1109/ICVC.1999.820830","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820830","url":null,"abstract":"Due to an efficient interconnect structure and internal parallelism, partitioned-bus architecture is viable for deep sub-micron chip design. In this paper, we propose a new partitioned-bus architecture and its supporting high-level synthesis methodology. The new architecture extends an existing linear architecture by stacking multiple layers for handling large datapath intensive applications. Experiments show that the approach generates compact datapath layout with flexibility of aspect ratio and reduces average bus driving length.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"52 1","pages":"81-84"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80835337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820996
Woo-Seung Yang, Hansoo Kim, Myoung-Cheol Shin, I. Park, C. Kyung
MPEG decoding chips have to support multiple features such as video stream decoding, transport stream parsing, multi-standard support, scan line conversion for on-screen display, and audio/video synchronization. Some of these features are computation-intensive, while others are size-intensive. In this paper an embedded processor specialized for the MPEG decoding is proposed to cope with the complicated requirements. The proposed processor can execute up to four operations at a time to handle intensive computation, and can change instruction issue rate according to the required performance in order to save code size which is very important in MPEG applications. In addition, the processor can switch tasks rapidly to keep the number of buffers existing between tasks minimal.
{"title":"A multi-threading MPEG processor with variable issue modes","authors":"Woo-Seung Yang, Hansoo Kim, Myoung-Cheol Shin, I. Park, C. Kyung","doi":"10.1109/ICVC.1999.820996","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820996","url":null,"abstract":"MPEG decoding chips have to support multiple features such as video stream decoding, transport stream parsing, multi-standard support, scan line conversion for on-screen display, and audio/video synchronization. Some of these features are computation-intensive, while others are size-intensive. In this paper an embedded processor specialized for the MPEG decoding is proposed to cope with the complicated requirements. The proposed processor can execute up to four operations at a time to handle intensive computation, and can change instruction issue rate according to the required performance in order to save code size which is very important in MPEG applications. In addition, the processor can switch tasks rapidly to keep the number of buffers existing between tasks minimal.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"496 1","pages":"545-548"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77802469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.821002
Ik-soo Eo, Seongbong Lee, Kyungsu Kim
WLL (wireless local loop) concerns the transmission of information without wire connection. This supplies voice, fax, and data services. The wireless communication system has the advantages of small construction time and high data rate service. For the air interface specification satisfaction we need a base station and terminal station. We design the base station modem, which is supports the Korean standard WLL system specification. The functions of the modem are forward modulation, reverse demodulation and deinterleaver and Viterbi decoder. We started with VHDL coding, carried out verification and synthesized the coding. The designed chip has 106000 gates and 7 kbits static RAM by 0.5 /spl mu/m CMOS standard cell technology.
{"title":"WLL base station modem ASIC","authors":"Ik-soo Eo, Seongbong Lee, Kyungsu Kim","doi":"10.1109/ICVC.1999.821002","DOIUrl":"https://doi.org/10.1109/ICVC.1999.821002","url":null,"abstract":"WLL (wireless local loop) concerns the transmission of information without wire connection. This supplies voice, fax, and data services. The wireless communication system has the advantages of small construction time and high data rate service. For the air interface specification satisfaction we need a base station and terminal station. We design the base station modem, which is supports the Korean standard WLL system specification. The functions of the modem are forward modulation, reverse demodulation and deinterleaver and Viterbi decoder. We started with VHDL coding, carried out verification and synthesized the coding. The designed chip has 106000 gates and 7 kbits static RAM by 0.5 /spl mu/m CMOS standard cell technology.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"25 1","pages":"566-569"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78034452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820983
S. Chae, K. Yoo, Byoung-Yong Park, S. Han, J. Ha, Jinwon Park
The plasma damage of gate oxides with the thickness of 45 and 35 /spl Aring/ was investigated using NMOS and PMOS devices with poly-Si antennas. Poly etch was performed in a magnetically enhanced reactive ion etcher (MERIE) reactor using Cl/sub 2//HBr chemistry. The transistors in the antenna test pattern had the antenna ratio of 5000:1. Among the antenna patterns used in this study, the comb type antenna devices suffered more from charging damage during poly-Si etching. Two different methods of wet and NO type were employed to grow the gate oxides. The wet and NO gate oxides were grown in O/sub 2/+H/sub 2/ and O/sub 2/ ambient followed by NO anneal, respectively. In the bar type antenna pattern with the small length/width ratio (dummy antenna), the dependences of plasma damage on poly-Si etching, ion implantation and annealing conditions were not observed, However evident charging damage behavior is observed in the NMOS transistors having comb antenna, which were affected more by charging damage during poly-Si etching. The results of plasma damage characterization indicated that the device structure with amorphous Si (grain size:3000 /spl Aring/) on NO gate oxide is more resistent to the plasma damage than that of fine grain Si (grain size:300 /spl Aring/) on wet gate oxide.
{"title":"Plasma induced charging damage on thin gate oxide","authors":"S. Chae, K. Yoo, Byoung-Yong Park, S. Han, J. Ha, Jinwon Park","doi":"10.1109/ICVC.1999.820983","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820983","url":null,"abstract":"The plasma damage of gate oxides with the thickness of 45 and 35 /spl Aring/ was investigated using NMOS and PMOS devices with poly-Si antennas. Poly etch was performed in a magnetically enhanced reactive ion etcher (MERIE) reactor using Cl/sub 2//HBr chemistry. The transistors in the antenna test pattern had the antenna ratio of 5000:1. Among the antenna patterns used in this study, the comb type antenna devices suffered more from charging damage during poly-Si etching. Two different methods of wet and NO type were employed to grow the gate oxides. The wet and NO gate oxides were grown in O/sub 2/+H/sub 2/ and O/sub 2/ ambient followed by NO anneal, respectively. In the bar type antenna pattern with the small length/width ratio (dummy antenna), the dependences of plasma damage on poly-Si etching, ion implantation and annealing conditions were not observed, However evident charging damage behavior is observed in the NMOS transistors having comb antenna, which were affected more by charging damage during poly-Si etching. The results of plasma damage characterization indicated that the device structure with amorphous Si (grain size:3000 /spl Aring/) on NO gate oxide is more resistent to the plasma damage than that of fine grain Si (grain size:300 /spl Aring/) on wet gate oxide.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"40 1","pages":"497-500"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72845599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820823
Sang-Hoon Lee, Dong-Yun Lee, Jin-Yang Kim, Young-Jin Gu, Young-Kwan Park, J. Kong
In this paper, we introduce a state-of-the-art statistical modeling technique which is developed in order to evaluate the sensitivity of chip performance with device parameters using SPICE simulation. ET-based SPICE modeling links the shift of E-tests (Electrical tests) to a set of SPICE model parameters without additional measurements of I-V curves. Therefore, it is very useful and quick in analyzing the sensitivity of circuit characteristics to E-tests. In the case of an asynchronous DRAM, PMOS Idsat primarily contributes to the variation of the chip performance tRAC. This methodology not only enables circuit designers to analyze the circuit sensitivity with E-test, but also provides key device characteristics for the statistical process control during the yield ramp-up.
{"title":"A new analysis technique for the sensitivity of chip performance","authors":"Sang-Hoon Lee, Dong-Yun Lee, Jin-Yang Kim, Young-Jin Gu, Young-Kwan Park, J. Kong","doi":"10.1109/ICVC.1999.820823","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820823","url":null,"abstract":"In this paper, we introduce a state-of-the-art statistical modeling technique which is developed in order to evaluate the sensitivity of chip performance with device parameters using SPICE simulation. ET-based SPICE modeling links the shift of E-tests (Electrical tests) to a set of SPICE model parameters without additional measurements of I-V curves. Therefore, it is very useful and quick in analyzing the sensitivity of circuit characteristics to E-tests. In the case of an asynchronous DRAM, PMOS Idsat primarily contributes to the variation of the chip performance tRAC. This methodology not only enables circuit designers to analyze the circuit sensitivity with E-test, but also provides key device characteristics for the statistical process control during the yield ramp-up.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"12 1","pages":"61-64"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81471756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-10-26DOI: 10.1109/ICVC.1999.820882
Sunyoung Kim, Sungwoong Chung, Joo-Han Shin, N. Park, J. K. Kim, J. Park
Low-k candidate SOG material HOSP(R) is evaluated and compared to HSQ. Particularly, the chemical nature of the film and the effects of various processing steps were investigated using FTIR, TDS, oscilloscope and stress gauge. The water absorption upon various post etch treatments turned out to be a crucial factor affecting the dielectric properties of the film. HOSP(R) proved to be a dielectric with lower k value compared to the HSQ film but was more vulnerable to moisture uptake.
{"title":"HOSP(R) as a low dielectric material: comparative study against hydrogen silsesquioxane","authors":"Sunyoung Kim, Sungwoong Chung, Joo-Han Shin, N. Park, J. K. Kim, J. Park","doi":"10.1109/ICVC.1999.820882","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820882","url":null,"abstract":"Low-k candidate SOG material HOSP(R) is evaluated and compared to HSQ. Particularly, the chemical nature of the film and the effects of various processing steps were investigated using FTIR, TDS, oscilloscope and stress gauge. The water absorption upon various post etch treatments turned out to be a crucial factor affecting the dielectric properties of the film. HOSP(R) proved to be a dielectric with lower k value compared to the HSQ film but was more vulnerable to moisture uptake.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"37 1","pages":"218-221"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86921792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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