Advanced Cu CMP defect excursion control for leading edge micro-processor manufacturing

Abstract

The introduction of yield sensitive, advanced interconnect technology coupled with the requirement for accelerating yield ramp in today's state-of-the-art semiconductor manufacturing facilities, are driving tool monitoring requirements for fast and accurate defect excursion control. In the Copper CMP module the challenge is accentuated by the relative immaturity of this process, the dominance of single wafer excursions and a high count of nuisance defect types relative to the critical yield-limiting defect types. A manufacturing-worthy Copper CMP tool monitor methodology is described here that improves excursion control through detection and tracking of critical, yield-limiting defect types, independent of non-yield-critical nuisance defect types. High-resolution automatic defect review and classification, a critical component of the methodology, is limited to wafers with high critical-defect counts, reducing monitoring cost and time-to-results. A new trigger sampling feature and intelligent image sampling reduces monitoring cost and time-to-results through minimizing defect review overhead. Integration of such a solution into the manufacturing environment is presented in detail and contrasted next to existing traditional defect excursion control model. Ease-of-use considerations are highlighted with use case examples. The paper will approximate the cost savings to manufacturing such as reducing existing levels of false excursion due to nuisance defects and improving the cycle time in the Cu CMP module. Benefits are achieved by integrating functionality into existing inspection hardware. No additional capital equipment was required.