A fast synchronous pipelined DRAM (SP-DRAM) architecture with SRAM buffers

Abstract

We propose a Synchronous Pipelined DRAM (SP-DRAM) architecture which has a fast row-cycle. Pipeline circuitry is inserted in the row path and multiple SRAM buffers are integrated in the DRAM to reduce row latency. The data transfer rate of the SP-DRAM is measured to be faster by 40% than SDRAM and by 20% than VCM as a result of system level performance analysis. A partial activation scheme is adopted in the cell core to reduce unnecessary power consumption. The SP-DRAM can maintain compatibility with a conventional SDRAM interface with negligible performance degradation.