Thermal stress control in Cu interconnects

Abstract

Grain growth of Cu interconnects in a low k dielectric was achieved at an elevated anneal temperature of 250 °C without stress voiding related problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional structure annealed at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects.